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Senior Physical Design Engineer
Mountain View, CA
Job Description
OverviewMicrosoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. Microsoft's Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products such as Xbox to high-performance Azure cloud servers, clients, and augmented reality.We are looking for a Senior Physical Design Engineer to work on leading edge Intellectual Property (IP) development as part of the Semi-Custom and Central Intellectual Property Silicon (SCIPS) team. The candidate should be a motivated self-starter who will thrive in this cutting-edge technical environment.Microsoft's mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond. In alignment with our Microsoft values, we are committed to cultivating an inclusive work environment for all employees to positively impact our culture every day. We're committed to a diverse and inclusive workplace and encourage applicants from all backgrounds and walks of life. Difference makes us better.
ResponsibilitiesMicrosoft's SCIPS organization develops various soft and hard IPs and you will have the opportunity to implement designs in Register Transfer Level (RTL) to Physical Design (PD) and RTL to Graphic Data Systems (GDS) flows. For RTL-to-PD, you will be a key link between front-end design and System on Chip (SOC) back-end teams. You will be responsible for implementing feedback and mitigations in the design constraints and toolchain to ensure best-in-class Power Performance Area (PPA.) In RTL-to-GDS, you will not only be responsible for the tasks mentioned in RTL-to-PD, but also floorplanning, place-and-route, and signoff for timing, Electro Migration and Voltage Drop (EMVD), and physical verification. Excellent communication skills will be needed to coordinate with RTL, Design for Test (DFT) Computer Aided Design (CAD) and SoC physical design teams.You will participate in flow development, design automation, and correlation exercises to back-end flows. You are expected to work with limited direction and have attention to detail. You will also be expected to be able to provide status of progress, issues, and risks on the program to the management team. OtherEmbody our Culture and Values
ResponsibilitiesMicrosoft's SCIPS organization develops various soft and hard IPs and you will have the opportunity to implement designs in Register Transfer Level (RTL) to Physical Design (PD) and RTL to Graphic Data Systems (GDS) flows. For RTL-to-PD, you will be a key link between front-end design and System on Chip (SOC) back-end teams. You will be responsible for implementing feedback and mitigations in the design constraints and toolchain to ensure best-in-class Power Performance Area (PPA.) In RTL-to-GDS, you will not only be responsible for the tasks mentioned in RTL-to-PD, but also floorplanning, place-and-route, and signoff for timing, Electro Migration and Voltage Drop (EMVD), and physical verification. Excellent communication skills will be needed to coordinate with RTL, Design for Test (DFT) Computer Aided Design (CAD) and SoC physical design teams.You will participate in flow development, design automation, and correlation exercises to back-end flows. You are expected to work with limited direction and have attention to detail. You will also be expected to be able to provide status of progress, issues, and risks on the program to the management team. OtherEmbody our Culture and Values
Job Summary
Company
Start Date
As soon as possible
Employment Term and Type
Regular, Full Time
Required Experience
Open
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