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Principal Physical Design Engineer
Mountain View, CA
Job Description
OverviewMicrosoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. Microsoft's Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality.We are looking for a Principal Physical Design Engineer to work on industry-leading, high-speed, mixed-signal interface IP development as part of the SCIPS (Semi-custom and Central IP Silicon) team. The candidate should be a motivated self-starter with the ability to lead others who will thrive in this cutting-edge technical environment.Microsoft's mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond. We're committed to a diverse and inclusive workplace and encourage applicants from all background and walks of life. Difference makes us better.
ResponsibilitiesWorking alongside IP architects and circuit designers to develop solutions that meet system-on-a-chip (SoC_ team requirements. Being responsible for all aspects of physical design including floorplanning, bump and ESD planning, synthesis, place-and-route, clock tree synthesis (CTS) and signoff for timing, electromigration & voltage drop, and physical verification. Integrating complex analog IPs within a digital system. Being a key interface between IP and SoC. Working with packaging engineers to understand IP requirements for 2D, 2.5D and 3D packaging options. Communicatiing to coordinate and drive collaboration with RTL, DFT, CAD and SoC teams. Provide technical direction to less-experienced physical design engineers.Work with limited direction and have attention to detail.Provide crisp status of progress, issues, and risks on the program to the management team.Embody our culture and values.
ResponsibilitiesWorking alongside IP architects and circuit designers to develop solutions that meet system-on-a-chip (SoC_ team requirements. Being responsible for all aspects of physical design including floorplanning, bump and ESD planning, synthesis, place-and-route, clock tree synthesis (CTS) and signoff for timing, electromigration & voltage drop, and physical verification. Integrating complex analog IPs within a digital system. Being a key interface between IP and SoC. Working with packaging engineers to understand IP requirements for 2D, 2.5D and 3D packaging options. Communicatiing to coordinate and drive collaboration with RTL, DFT, CAD and SoC teams. Provide technical direction to less-experienced physical design engineers.Work with limited direction and have attention to detail.Provide crisp status of progress, issues, and risks on the program to the management team.Embody our culture and values.
Job Summary
Company
Start Date
As soon as possible
Employment Term and Type
Regular, Full Time
Required Experience
Open
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