ASIC/ FPGA Design Verification Engineer
El Segundo, CA 
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Posted 13 days ago
Job Description
Title: ASIC/ FPGA Design Verification Engineer
Location: El Segundo, CA
Duration: 6 Months

Required Skills:

* 5+ years of experience
* 1-2 years of UVM tool
* Cadence Xcelium verification tool

Job Description:
Create UVM simulation plan from design specification. Create or modify UVC, Score Board, Monitor, and test cases. Verify until functional coverage and code coverage meet project threshold. Document results.

Education: Must have min Bachelor's in Engineering
Additional Details: Must have min 5 years of experience. UVM experience is important and required.

Successful completion of training is a contingency for this assignment - OJT or formal classroom training.

Notice to California Applicants: SPECTRAFORCE is committed to complying with the California Privacy Rights Act ("CPRA") effective January 1, 2023; and all data privacy laws in the jurisdictions in which it recruits and hires employees. A Notice to California Job Applicants Regarding the Collection of Personal Information can be located on our website. Applicants with disabilities may access this notice in an alternative format by contacting .

SPECTRAFORCE is an equal opportunity employer and does not discriminate against any employee or applicant for employment because of race, religion, color, sex, national origin, age, sexual orientation, gender identity, genetic information, disability or veteran status, or any other category protected by applicable federal, state, or local laws. Please contact Human Resources at nahr@spectraforce.com if you require reasonable accommodation.

 

Job Summary
Start Date
As soon as possible
Employment Term and Type
Regular, Full Time
Required Education
Bachelor's Degree
Required Experience
5+ years
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